FIG. 9 is the block diagram of a conventional clock generation circuit as an example. With referring to the figure, a reference numeral 1 denotes a reference signal, a reference numeral 3 denotes a selection signal selecting one of a plurality of reference signals, a reference numeral 4 denotes a selection circuit, a reference numeral 5 denotes a PLL circuit, and a reference numeral 6 denotes a generated clock. The PLL circuit is configured with the following elements. A reference numeral 21 denotes a phase comparator, a reference numeral 22 denotes a low-pass filter, a reference numeral 23 denotes an amplifier, a reference numeral 24 denotes a reference voltage generator, a reference numeral 25 denotes a voltage control oscillator, and a reference numeral 26 denotes a divider.
The operation is now described. A plurality of reference signals 1 are inputted, and one of the plurality of reference signals is selected in the selection circuit 4 based on the selection signal 3. FIG. 9 shows the case of inputting two reference signals 1a and 1b for explanation. Then, the phase of a selected reference signal land the phase of a signal outputted from the divider 26 are compared in the phase comparator 21. The phase comparator 21 outputs a signal corresponding to a phase difference between the selected reference signal and the output signal from the divider 26. This phase difference signal is smoothed through the low-pass filter 22, and a voltage potential difference between this signal and the reference voltage generator 24 is amplified in the amplifier 23. The output voltage of the amplifier 23 activates the voltage control oscillator 25 to output the clock signal 6 whose phase is synchronized with the phase of the selected reference signal 1. The divider 26 divides the generated clock 6 to generate the signal whose phase is to be compared with the phase of the reference signal 1.
FIG. 10 shows the reference signals 1, an output from the selection circuit 4 that is selected based on the selection signal 3, the generated clock 6, and an output signal from the divider 26. At 1001 in FIG. 10, it is illustrated that a reference signal 1a is selected in the selection circuit 4 based on the selection signal 3, and the divider 26 and the generated clock 6 are both synchronized with the reference signal 1a. 
With 1002 in FIG. 10, it is illustrated that a reference signal 1b is selected upon change of the selection in the selection circuit 4 based on the selection signal 3. In this state, the generated clock 6 and the output of the divider 26 are both out of phase with the reference signal 1b just selected. The phase comparator 21 outputs a phase difference signal in commensurate with this phase difference. The phase difference signal is then smoothed through the low-pass filter 22, and amplified through the amplifier 23 to control the transmission frequency of the voltage control oscillator 25 so that the phase of the output of the divider 26 and the phase of the reference signal 1b selected in the selection circuit 4 match.
At 1003 in FIG. 10, it is illustrated that the generated clock 6 and the output of the divider 26 are both synchronized with the reference signal 1b changed through the circuit operation mentioned above.
With the conventional circuit, it is needed to control the reference voltage generator 24 so as to match the phase of the selected reference signal 1 and the phase of the generated clock 6. In steady state, phase difference between the selected reference signal 1 and the generated clock 6 is called steady-state phase difference. The phase difference may be reduced by increasing the loop gain of the PLL circuit 5. However, the problem is that the transient phase fluctuation of the generated clock 6 gets large because it is affected by the change in phase of the reference signal 1 upon change of the reference signal 1. There is a tradeoff relation between the steady-state phase difference and the size of the phase fluctuation of the generated clock 6 upon change of the reference signal 1.
Further, it is hard to integrate the low-pass filter 22 for enhancing filter precision performance because the low-pass filter 22 is generally configured with such as a resistance and a capacitor. As the voltage control oscillator 25, there is VCXO (Voltage Controlled Xtal Oscillator) using crystal or VCO (Voltage Controlled Oscillator) using coils and capacitors. It is difficult to integrate VCXO. With VCO, its modulation sensitivity is so high that loop gain gets high in the PLL circuit. Therefore, the problem is that the phase fluctuation of the generated clock becomes large upon change of the reference signal.
The conventional clock generation circuit, thus configured, needs to control the reference voltage generator for matching the phase of the reference signal and the phase of the generated clock. And there is a problem that it is difficult to integrate the low-pass filter or the voltage control oscillator in the case of high precision control of the steady-state phase difference or the transient response upon change of the reference signal. Still another problem is that the transient response upon change of the reference signal depends upon loop gain in the PLL circuit and the time constant of the low-pass filter, so that high design flexibility cannot be achieved.
The present invention is directed to solving the problems discussed above. It is an object to eliminate control involved to match the phase of the reference signal and the phase of the generated clock, make it possible to integrate all the circuit elements, enable high precision transient response control upon change of the reference signal, and achieve high design flexibility.